A Level Computer Science 9618 4.1.1 CPU Architecture

Exam focused learning objectives

Explain the Von Neumann model and stored program concept using correct CPU terminology.
Apply knowledge of registers, buses, and the fetch execute cycle to trace data movement in a computer system.
Assess how processor characteristics such as cores, clock speed, bus width and cache affect performance in different scenarios.
Evaluate the role of interrupts and interrupt handling in improving CPU efficiency and responsiveness.
Explain how ports and system components support input and output and how they appear in exam questions.

Big picture overview

CPU architecture is about how the processor works internally and how data moves through the system. The best exam answers connect four ideas:

Structure the Von Neumann model, CPU parts, registers, buses, clock, memory.
Process the fetch execute cycle and register transfer notation.
Performance factors such as cores, cache, clock speed, and bus width.
Control and efficiency interrupts, interrupt service routines, and handling during execution.

In exams, these ideas are often tested through: definition questions, sequence questions, label and explain questions, scenario based application, and evaluate questions asking which CPU feature is best for a given use case.

Subtopic	What it tells you	Why it is exam useful
CPU architecture	How the processor is built and controlled	Used in explain and label questions
Fetch execute cycle	How instructions are processed	Common sequence and trace questions
Performance factors	What makes one CPU faster or more suitable than another	Frequent compare and assess questions
Interrupts	How the CPU responds to urgent events	Often tested with real world scenarios

1. Von Neumann model and stored program concept

Plain English first: a computer stores both data and instructions in the same main memory, and the CPU fetches and executes instructions one at a time.

Accurate terminology: the Von Neumann architecture uses a single memory for instructions and data. The CPU communicates with memory over shared buses. The stored program concept means the program instructions are held in memory in binary and executed sequentially unless a branch changes the flow.

Feature	Meaning	Exam tip
Single memory	Instructions and data stored together	Explain the bottleneck and why access can slow down
Stored program	Program is stored in memory like data	Link to how software is loaded and executed
Sequential execution	Instructions usually run in order	Mention branch instructions and interrupts

Exam useful point: The Von Neumann bottleneck is the limited speed of data transfer between CPU and memory because the same pathway is shared. This is a common evaluation point when discussing why cache, wider buses, and faster memory matter.

Video support

Watch a short explanation of the Von Neumann architecture before moving on.

2. CPU registers, ALU, CU, system clock and immediate access store

Plain English first: registers are tiny, very fast storage locations inside the CPU. They hold addresses, instructions, data, and results while the CPU works.

Accurate terminology: registers are high speed storage elements used during instruction execution. The main registers you need are:

Register	Full meaning	Function	Exam memory hook
PC	Program Counter	Holds address of next instruction	Points to the next step
MAR	Memory Address Register	Holds address being accessed	Address goes here first
MDR	Memory Data Register	Holds data or instruction being transferred	Data passes through it
CIR	Current Instruction Register	Holds current instruction being decoded and executed	Current task
ACC	Accumulator	Stores intermediate arithmetic and logic results	Accumulator accumulates results
IX	Index Register	Used in indexed addressing and loops	Adds an offset
Status Register	Flags Register	Stores condition flags like zero, carry, negative, overflow	Shows what happened last

Component	Role	Exam usefulness
ALU	Carries out arithmetic and logical operations	Used in arithmetic and logic explanations
CU	Controls fetch, decode, execute and data movement	Mention in register transfer and cycle questions
System clock	Provides regular timing pulses	Links to clock speed and performance
Immediate Access Store	Main memory used for programs and data being actively processed	Connect to fetch instruction source

Why this matters in exams: Many marks are lost because students say register functions too vaguely. Use precise language: PC holds the address of the next instruction, not just PC stores instructions.

3. Address bus, data bus and control bus

Plain English first: the CPU needs three different paths to communicate with memory and devices: one for addresses, one for data, and one for control signals.

Bus	Direction	Carries	Exam phrase
Address bus	Usually one way from CPU	Memory or device address	Identifies where data is needed from
Data bus	Two way	Data and instructions	Transfers actual data
Control bus	Two way	Control signals such as read, write, clock, interrupt	Coordinates operations

Performance factors

Factor	Effect	Evaluation point
Processor type	Different designs suit different tasks	A specialist processor may outperform a general purpose CPU for one job
Cores	More cores can process more tasks simultaneously	Best when software is multi threaded
Bus width	More bits transferred at once	Can improve throughput, but only if other parts keep up
Clock speed	More cycles per second	Not always best alone because architecture matters too
Cache memory	Stores frequently used data close to CPU	Often the biggest practical speed booster

Evaluation toolkit: When asked which CPU is better, do not say only faster clock speed means better. Consider task type, software optimisation, multitasking, cache size, and bottlenecks.

4. Ports: USB, HDMI and VGA

Plain English first: ports are connection points used to attach external devices such as keyboards, storage devices, displays, and projectors.

Port	Typical use	Exam point
USB	Connects peripherals and storage	Versatile, common, can carry data and power
HDMI	Digital audio and video output	Higher quality modern display connection
VGA	Analogue video output	Older technology, lower quality than digital connections

5. Fetch execute cycle and register transfer notation

Plain English first: the CPU repeatedly fetches an instruction, works out what it means, and then carries it out.

Accurate terminology: the fetch execute cycle is the repeated process used by the CPU to retrieve instructions from memory, decode them, and execute them. Register transfer notation is a shorthand way of showing how data moves between registers.

Stage	What happens	Typical register movement
Fetch	Instruction address is sent to memory, instruction returned	PC to MAR, memory to MDR, MDR to CIR, PC increments
Decode	CU interprets the instruction	CIR examined by CU
Execute	Instruction carried out	ALU, ACC, memory or I O involved depending on instruction

Example register transfer notation:

MAR ← PC means the address in the PC is copied to the MAR.
MDR ← memory[MAR] means data at the memory address in MAR is loaded into MDR.
PC ← PC + 1 means the next instruction address is prepared.

Common exam pitfall: students often mix up MAR and MDR. Remember: address goes to MAR, data goes to MDR.

Video support

Use this to reinforce the fetch execute cycle and register movement.

6. Interrupts, ISR, causes, applications and handling during the fetch execute cycle

Plain English first: an interrupt is a signal that tells the CPU to stop what it is doing, deal with something urgent, and then return to the original task.

Accurate terminology: an interrupt causes the CPU to temporarily suspend the current program, save its state, and execute an interrupt service routine (ISR) before resuming normal execution.

Interrupt cause	Example	Why it matters
Hardware interrupt	Printer ready, key press, timer signal	Improves responsiveness and lets CPU react to external events
Software interrupt	Program requests operating system service	Used for controlled access to system functions
Fault / error	Divide by zero, hardware error	Stops incorrect processing or allows recovery

Interrupt handling step	What the CPU does
1. Finish current instruction	CPU usually completes the current instruction first
2. Save state	Stores PC and status so it can return later
3. Identify interrupt	Checks interrupt type and priority if necessary
4. Run ISR	Executes the code that handles the event
5. Restore state	Returns saved values and resumes interrupted program

Applications of interrupts:

Keyboard input so the CPU can respond when a key is pressed.
Printer signals when it is ready for more data.
Timer interrupts for scheduling and multitasking.
Error handling when hardware or software faults occur.

Evaluation toolkit for interrupts:

Strength: CPU time is not wasted constantly checking devices.
Strength: Improves responsiveness and supports multitasking.
Weakness: Interrupt handling adds overhead because the CPU must save and restore state.
Weakness: Too many interrupts can reduce efficiency.
Effectiveness: Best for events that occur unpredictably.

Exam ready phrases: Interrupts improve processor efficiency because the CPU can continue with useful work until an event needs attention.
However, frequent interrupts create overhead because the system must save context and run the ISR.

How these topics are assessed in exams

Question type	Typical marks	What examiners want	Common pitfalls
Define or state	1 to 2	Precise terms	Too vague, missing key word
Explain a process	3 to 6	Clear sequence and correct register movement	Wrong order, confusing registers
Compare or assess	4 to 8	Balanced points with judgement	One sided answer, no conclusion
Scenario based application	4 to 10	Use given context and justify choice	Rewriting theory without applying to scenario
Evaluate	6 to 12	Strengths, weaknesses, and final judgement	No conclusion, no comparative judgement

Scenario based application questions with model answers

Question 1: A school computer starts printing a document while the user continues typing in another program. Explain how interrupts help the computer manage both tasks.

Model answer: The printer uses an interrupt when it is ready for more data, so the CPU does not need to keep checking it constantly. The CPU saves the current state, runs the interrupt service routine to handle the printer, then restores the saved values and continues the original program. This improves efficiency and responsiveness.

Question 2: A student wants a CPU for video editing. Which performance factors should be considered and why?

Model answer: A CPU with multiple cores is useful because video editing software can split work across threads. A larger cache can improve speed by keeping frequently used data close to the processor. A higher clock speed can help, but it is not enough on its own because software design and cache size also affect performance. Wider buses may also improve throughput by transferring more data at once.

Annotated model exam answer

Question: Explain how the fetch execute cycle uses registers and buses to process an instruction. [6]

Model answer with annotation:

The program counter holds the address of the next instruction, and this address is copied to the MAR. [AO1] correct register knowledge
The address is sent along the address bus to memory, and the instruction at that address is returned on the data bus into the MDR. [AO1] accurate bus function
The instruction is copied from the MDR to the CIR, where it is decoded by the control unit. [AO1] process explanation
The CPU then executes the instruction, for example using the ALU if it is an arithmetic instruction. [AO2] applying to an operation
This process is efficient because the CPU can fetch and execute instructions rapidly, but the shared pathway between memory and CPU can create a bottleneck if memory access is slow. [AO3] evaluation of limitation

Why this is high scoring: It uses correct sequence, precise register names, bus terminology, an application example, and a short evaluation point.

Retrieval practice

Quick definition checks

What is the stored program concept?
What is the function of the MAR?
What does the ACC do?
What is the role of the control bus?
What is an ISR?
Why does cache memory improve performance?

Model answers

Stored program concept: instructions and data are both stored in main memory in binary.
MAR: stores the address of the memory location being accessed.
ACC: stores intermediate and final results of arithmetic and logic operations.
Control bus: carries control signals such as read, write, clock and interrupt.
ISR: the program that handles an interrupt.
Cache: keeps frequently used data close to the CPU, reducing access time.

Explain in 30 seconds prompts

Explain the difference between the address bus and data bus.
Explain why interrupts improve efficiency.
Explain how a higher clock speed can help, but is not always enough.
Explain why the Von Neumann architecture can create a bottleneck.

Model answers:

Address bus vs data bus: the address bus carries where data should go or come from, while the data bus carries the actual data or instruction.
Interrupts: they let the CPU deal with important events immediately instead of constantly checking devices.
Clock speed: a faster clock can increase the number of cycles per second, but overall performance also depends on cache, cores and architecture.
Von Neumann bottleneck: instructions and data share the same pathway to memory, which can slow down transfer.

Final revision summary

Von Neumann: one memory for data and instructions; stored program concept; sequential execution.
Registers: PC next instruction, MAR address, MDR data, CIR current instruction, ACC results, IX offset, Status Register flags.
ALU and CU: ALU processes calculations and logic; CU controls operations and timing.
Buses: address bus carries address, data bus carries data, control bus carries signals.
Performance: compare cores, clock speed, cache, bus width, and processor type in context.
Ports: USB versatile, HDMI digital audio video, VGA analogue and older.
Fetch execute: fetch, decode, execute in correct order using register transfers.
Interrupts: cause CPU to pause current task, save state, run ISR, then resume.
Evaluation points: efficiency, bottleneck, overhead, multitasking, suitability for task.

Top exam advice: For full marks, write in the order the CPU actually works, use exact register names, and always link performance claims to the scenario. High scoring answers do not just describe features, they explain effects and make a justified judgement.